The present invention relates to the field of circuit simulators and in particular to signal integrity analysis of simulated circuits.
A circuit simulator is a device, data processing system, or computer program that represents features of the behaviour of a physical circuit using abstract models of the physical circuit. The solution to any problem involving circuit-level simulation by a simulator involves analyzing the circuit.
Signal integrity testing is an analysis to check the quality of the signal propagating through a transmission line from a driver end to a receiver end. The analysis checks whether the signal waveform arriving at the receiving end is the same as the waveform at the driver end. In a typical signal integrity analysis using an Automated Network Design Analysis Program (ANDAP) or AS/X models (involving the simulation AS/X net or ANDAP net which calls an input/output IO Cell), the time taken to simulate a particular net with respect to either best case/worst case is high. AS/X is a tool used to do the simulations. This simulation time depends on the transistor level circuit of the IO cells.
FIG. 1 is a transistor level diagram illustrating an ANDAP net 100 obtained using standard libraries. The net list 100 includes 12 MOSFETs, of which 6 transistors are PMOS transistors 110-120 and the remaining 6 are NMOS transistors 130-140. The PMOS transistors 110-120 share a common GATE G14. The NMOS transistors 130-140 also share a common GATE G24. The source of each PMOS transistor 110-120 is coupled to the supply voltage VDD. Similarly, the source of each NMOS transistor 130-140 is coupled to ground. The drain of each PMOS transistor 110-120 is coupled to a corresponding one of the NMOS transistors 130-140. For example, the drains of PMOS transistor 110 and NMOS transistor 130 are coupled together. Similarly, the drain of PMOS transistor 112 is coupled to that of NMOS transistor 132, and so on. A current IDS flows through the configuration of transistors from the supply voltage VDD to the ground terminal through the parallel configurations of transistors.
In FIG. 1, the following parameters appertain:
The effective channel length is 0.18 micrometers and the channel length is 0.24 micrometers. PWp and PWn are the channel width of PMOS and NMOS transistors. PLp and PLn are the channel length of those transistors.
In signal integrity testing, the ANDAP net or AS/X net being simulated calls a particular IO cell. Internally these IO cells contain many transistors along with resistances and capacitances. So, the time to simulate such a net is high. The signal integrity analysis time for a large network 100 is high because of the large number of transistors 110-120, 130-140 that need to be simulated to arrive at the final result. The existing method of ASX, SPICE, or ANDAP simulation involves:
1. Simulating all the PMOS transistors individually; and
2. Simulating all the NMOS transistors individually.
Therefore, a need clearly exists for an improved system of performing signal integrity analysis for large circuit networks undergoing circuit simulation.
In accordance with a first aspect of the invention, there is provided a method of reducing simulation time taken by a central processing unit (CPU) during signal integrity analysis. In the method, a circuit network is provided for simulation having a plurality of transistors. A simplified circuit network having a reduced number of transistors is generated from the provided circuit network. The provided circuit network may be an ANDAP, SPICE, or ASX net. Transistors having the same channel length and being configured similarly from the provided circuit network are replaced by a single transistor having corresponding aggregate characteristics for the replaced transistors. Preferably, the transistors are configured in parallel. The provided circuit network is simulated using the simplified circuit network.
In accordance with a second aspect of the invention, there is provided an apparatus for reducing simulation time taken by a central processing unit (CPU) during signal integrity analysis. The apparatus includes a device for providing a circuit network for simulation_having a plurality of transistors, and a device for generating a simplified circuit network having a reduced number of transistors from the provided circuit network, where transistors having the same channel length and being configured similarly from the provided circuit network are replaced by a single transistor having corresponding aggregate characteristics for the replaced transistors.
In accordance with a third aspect of the invention, there is provided a computer program product having a computer readable medium having a computer program recorded therein for reducing simulation time taken by a central processing unit (CPU) during signal integrity analysis. The computer program product includes a computer program code module for providing a circuit network for simulation having a plurality of transistors, and a computer program code module for generating a simplified circuit network having a reduced number of transistors from the provided circuit network, where transistors having the same channel length and being configured similarly from the provided circuit network are replaced by a single transistor having corresponding aggregate characteristics for the replaced transistors.